`timescale 1ns/1ps
module test_tb;
	reg 	a,b,c;
	wire	d;
	
	test U1(.a(a),.b(b),.c(c),.d(d));
	
	initial begin
		a=1;b=1;c=1;
	#5	a=1;b=0;
	#5 	a=0;b=1;
	#5	a=0;b=0;
	#5	a=1;b=1;c=0;
	#5	a=1;b=0;
	#5 	a=0;b=1;
	#5	a=0;b=0;
	end

endmodule